The current generation of flash memory chips store as much as 32 billion bits on a chip .But that technology is likely to become increasingly problematic as chip makers struggle to reach ever finer dimensions.
Reached for comment later last week, Vivek Subramanian, an associate professor of electrical engineering at the University of California, Berkeley, who has read the technical paper describing the project, said, Everybody recognizes that scaling flash is going to be a problem in the long run. This looks like a really attractive technology that is both scaleable and consumes little power.
Industry executives said that the new materials might bolster the computer and consumer electronics industries just when it appeared they were nearing fundamental engineering limits.
This is a Christmas present for the industry because it shatters so many things at once, said Richard Doherty, president of Envisioneering, a computer industry consulting firm in Seaford, N.Y.,who has been briefed on the technical paper. This could change the basic equation between processors, local storage and communications.
Today s flash memories are largely divided into two distinct types called NOR and NAND, with different performance characteristics. The principal disadvantage of the flash design is that data cannot be addressed one bit at a time but only in larger blocks of data.
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